Analog to digital converters (ADCs) sample an analog signal and convert it into digital codes representing the signal's voltage. ADCs are typically driven by an external clock signal that controls the rate at which the sampling and conversion occurs. Typically, there is a trade off between clock speed and resolution; as the clock rate of the ADC is increased to accommodate higher bandwidth analog signals, the ADC has less time to convert new samples, which may lead to lower resolution.
This lower resolution may be caused by a lack of time needed to convert the analog sample into a full set of digital output bits. As the resolution and number of digital bits in the ADC output codes increase, the likelihood that the analog input signal will be closer to a digital code transition edge also increases. The amount of time needed to convert each bit may vary from bit to bit and cycle to cycle. For instance, more time may be required to resolve sampled signal values that are closer to transition edges. Each of these factors may affect the number of bits resolved in a given clock cycle.
Thus, as the clocking rate is increased in an ADC, the output resolution typically decreases. In some instances a clock rate may not provide the ADC with sufficient time to resolve a full set of digital output bits. In these instances, one or more of the least significant bits of the digital codes in a given sampling cycle may not be resolved and missing codes may result, as shown in FIG. 3A. Manufacturers may intentionally lower ADC clock rates to ensure that the ADC output does not include any missing code because the ADC had insufficient time to resolve the full set of digital output bits.
In some instances, such as in the conversion of analog image sensor data to digital codes, these missing codes may reduce the number of available colors represented in the digital codes. This may result in sharper and less smooth color transitions between different pixels. Additionally, in imaging systems, the noise threshold may increase as the level of detail captured by the image sensor increases. Thus, a larger image signal input may be able to support additional noise in the processed image without negatively affecting picture quality.
There is thus a need to operate ADCs at faster clock rates while reducing missing codes even if some bits do not get resolved.